Samsung presented its updated memory roadmap at SEMICON Taiwan 2026, with HBM5 and the upcoming zHBM architecture being the ...

Matrix is tackling the 3D DRAM heat problem by stacking memory beneath the XPU, but atomic-level flatness remains a brutal ...

Samsung Electronics on Tuesday showcased its 3D architecture strategy to break through current limitations in memory chip ...

Samsung HBM5 targets twice the overall performance of HBM4E, with 20 percent better efficiency and 20 percent lower thermal ...

NVIDIA NVHBM moves the HBM memory controller off the AI accelerator die and buries it inside the memory stack itself, freeing ...

Artificial intelligence is creating a growing memory bottleneck, with Bernstein analysts saying demand is spreading beyond high-bandwidth memory into conventional DRAM, NAND flash and storage.

NVIDIA says NVHBM can deliver up to 30% more memory bandwidth than HBM4E while cutting HBM power consumption by roughly 15 ...

SK Hynix has started building a $4B advanced packaging plant in Indiana. Europe approved state aid for the same kind of ...

The next phase of AI will be determined by whether the infrastructure can deliver intelligence reliably, economically and at ...

Thinner dies, more TSV area, thermal dissipation, and limited manufacturing capacity make HBM scaling much more difficult.

At Hot Chips 2026, Intel has revealed a few more technical details about the Xe3P architecture and its Crescent Island chip based on it.

Nvidia announced Nvidia Jetson Orin Nano 2, a new robotics computer set to redefine entry-level The big AI chip company said ...