A new technical paper titled “Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators” was ...

Using a signal integrity simulator to find the optimal interconnect topology and termination for a given situation.

Semiconductor policies, funding, and competitions are enabling industry and academia to pursue breakthroughs amidst the quest ...

Understanding Language Model Capabilities in Formal Verification of Digital Hardware” was published by researchers at UC Berkeley and NVIDIA. Abstract “The remarkable reasoning and code generation ...

Hybrid Speculative Vulnerability Detection” was published by researchers at Technical University of Darmstadt and Texas A&M University. “We introduce Specure, a novel pre-silicon verification method ...

Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes can help engineers partition and prioritize data movement, particularly in heterogeneous ...

Industry learning expands as more SoCs are disaggregated at leading edge, opening door to more third-party chiplets.

Custom hardware tailored to specific models can unlock performance gains and energy savings that generic hardware cannot ...

Finding out if a processor implementation matches the specification is important, but conformance testing is currently not ...

A technical paper titled “Impact of external magnetic fields on STT-MRAM” was recently published by researchers at Univ.

A technical paper titled “Programmable phase change materials and silicon photonics co-integration for photonic memory ...

Hardware-assisted verification; ultra high-density interconnects; generating PCB documentation; errors in ESD verification.